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SC1006

Computer Organisation and Architecture

Addressing Modes

4 Addressing Modes

Addressing Modes refers to how data is accessed, so that CPU can identify the actual operand or address location where operand is stored.

  1. Immediate data

  2. Register direct

  3. Register indirect

  4. Register indirect with offset

  5. Register indirect with index register

  6. Pre and post auto-indexing

4.1 Register Direct

[MOV] Copy data from operand on the right to operand on the left.
Any of the 16 registers in the processor can be an operand.

Execution of register direct instruction involves no access to memory.

4.2 Immediate Addressing

Source operand can be a constant value, that is copied into destination operand.
32-bit ARM instruction has 12-bits for the immediate value.

The 8-bit immediate value must be between 0 to 255.

That value is rotated right by 2n2n bits, where nn is the value of the 4 rotate right bits. Hence range of rotation is 0,2,4,…,300, 2, 4, \ldots, 30.

Therefore, to check if a 32-bit hexadecimal number can be an immediate value:

  1. The ’1’ bits must be maximum of 8 bits apart.
    E.g. 0x111 =...0001000100012= ... 0001\:0001\:0001_2. The furthest ’1’s are separated by 9 bits, so 0x101 cannot be an immediate value.

  2. The 8 bit immediate can only be rotated by an even number of bits.
    E.g. 0x102 =...0001000000102= ... 0001\:0000\:0010_2. The 8-bit immediate value would be 100000011000\:0001, which has to be ROR by 31 bits (not even number). Hence, 0x102 cannot be an immediate value.

Some immediate values cannot be stored.

Exeuction of immediate addressing involves no access to memory.

Only a subset of immediate values is available since data is encoded within fixed-length instruction.

4.3 Register Indirect with Base Register

4.3.1 LDR Instruction

Source operand register stores an address.

Data is fetched from that address in memory and coped into the destination operand.

4.3.2 STR instruction

Destination operand (on the right) stores an address.

Data in source operand (on the left) is copied into that address in memory.

4-byte data being read or written to memory must start at address that is multiple of 4.

Otherwise, there may be performance degradation issues.

4.4 Register Indirect with Offset

Offset applied to address stored in indirect register (source operand).
Data in array accessed with respect to base address (BA).
C program - First and last element of array = 7.
Assembly - Offset of 16 to store 7 at first and last element.

Note: When computing offset, each integer element occupies 4 bytes in memory.

Offset addressing does not change the indirect register’s content.

Used when the position of array element is known when coding the program.

4.5 Register Indirect with Index Register

C program - Initialise all 400 elements in array to zero.
Assembly - R1 (index register) continually incremented by 4.

Base (indirect) register’s content is not changed, but index register’s (R2) value can be modified.

Used if array position is to be computed during run time.

4.6 Register Indirect with Autoindexing

Aim is to modify the indirect register’s content.

Pre-index - Indirect register is autoindexed BEFORE computing effective address.
Post-index - Indirect register used to compute effective address BEFORE being autoindexed.
Preindex - Storing into R0 with effective address of R2 plus offset 4. EA then stored in R2.
Postindex - Storing into R0 with effective address of R2. R2 is then offset by 4 and stored in R2.

4.7 Stacks

Stack Pointer (SP)/R13 in ARM processor maintains the system stack.

The 4 possible stack implementations:

  1. Full Descending

  2. Full Ascending

  3. Empty Descending

  4. Empty Ascending

FD stack implementation:

Full: SP points to top item of stack.

Descending: Stack grows towards lower memory addresses.

LDR R0, [R13]; R13 stores address to top item in stack.
Preindexing used to jump 4 bytes, then store the data from source operand.
Postindexing used to store data in destination, then jump to new top of stack.

EA stack implementation:

Empty: SP points to unoccupied stack space.

Ascending: Stack grows towards higher memory address.

LDR R0, [R13, #-4]; Offset to get the lowest address of top item.
Postindexing used to store data at lowest address, then jump 4 bytes up.
Preindexing used to jump to lowest address of top item, then pop it to destination register.

4.8.1 Absolute Jump

Loading the actual address into PC.

Loading a new address into PC will alter the sequence of program execution.

Absolute jump is not position-independent. If the whole chunk of code memory was shifted, the code would fail.

4.8.2 Relative Jump

Telling the PC to jump to CodeB.

Due to FETCH-DECODE-EXECUTE pipeline architecture of the ARM processor, the PC points 8 bytes ahead of the current executed intsruction.

At 0x0500x050, the PC value during execution is 0x0580x058. To jump to CodeB at 0x0600x060, the offset applied is 0x060−0x058=0x0080x060-0x058=0x008.

4.8.3 Position-independent code

Relative jump supports position-independent code.

Position-independent (P-I) code doesn’t hardcode the address, instead a signed offset is calculated relative to the PC.
Destination and middle operands must be registers, rightmost operand can be a register or immediate value.

-bit instruction: 4-bits for condition flag, 8-bits for opcode, 4-bits for each register, hence only 12-bits left for only one immediate value.

PC-relative addressing used to access variables in data segment in memory.